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1/12 august 2004 high speed: f max = 180mhz (typ.) at v cc = 3.3v 5v tolerant inputs input voltage level: v il =0.8v, v ih =2v at v cc =3v low power dissipation: i cc = 4 a (max.) at t a =25c low noise: v olp = 0.3v (typ.) at v cc = 3.3v symmetrical output impedance: |i oh | = i ol = 4ma (min) balanced propagation delays: t plh ? t phl operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) pin and function compatible with 74 series 174 improved latch-up immunity power down protection on inputs description the 74lvx174 is a low voltage cmos hex d-type flip flop with clear non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power, battery operated and low noise 3.3v applications. information signals applied to d inputs are transferred to the q outputs on the positive going edge of the clock pulse. when the clear input is held low, the q outputs are held low independently of the other inputs. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v system. it combines high speed performance with the true cmos low power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvx174 low voltage cmos hex d-type flip-flop with clear with 5v tolerant inputs figure 1: pin connection and iec logic symbols table 1: order codes package t & r sop 74lvx174mtr tssop 74LVX174TTR tssop sop rev. 3
74lvx174 2/12 figure 2: input equivalent circuit table 2: pin description table 3: truth table x : don?t care figure 3: logic diagram this logic diagram has not be used to estimate propagation delays pin n symbol name and function 1clear asynchronous master reset (active low) 2, 5, 7, 10, 12, 15 q0 to q5 flip-flop outputs 3, 4, 6, 11, 13, 14 d0 to d5 data inputs 9 clock clock input (low-to-high, edge triggered) 8 gnd ground (0v) 16 v cc positive supply voltage inputs outputs function clear dclockq l x x l clear hl l hh h hx q n no change
74lvx174 3/12 table 4: absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. table 5: recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2.0v table 6: dc specifications symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current - 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 2) (v cc = 3.3v) 0 to 100 ns/v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 2.0 2.0 2.0 3.6 2.4 2.4 2.4 v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 0.8 0.8 0.8 3.6 0.8 0.8 0.8 v oh high level output voltage 2.0 i o =-50 a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 a 2.9 3.0 2.9 2.9 3.0 i o =-4 ma 2.58 2.48 2.4 v ol low level output voltage 2.0 i o =50 a 0.0 0.1 0.1 0.1 v 3.0 i o =50 a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 i i input leakage current 3.6 v i = 5v or gnd 0.1 1 1 a i cc quiescent supply current 3.6 v i = v cc or gnd 44040 a
74lvx174 4/12 table 7: dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. table 8: ac electrical characteristics (input t r = t f = 3ns) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low 2) parameter guaranteed by design (*) voltage range is 3.3v 0.3v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l = 50 pf 0.3 0.8 v v olv -0.8 -0.3 v ihd dynamic high voltage input (note 1, 3) 3.3 2 v ild dynamic low voltage input (note 1, 3) 3.3 0.8 symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time clock to q 2.7 15 7.6 14.5 1.0 17.5 1.0 18.5 ns 2.7 50 10.1 18.0 1.0 21.0 1.0 22.0 3.3 (*) 15 5.9 9.3 1.0 11.0 1.0 12.0 3.3 (*) 50 8.4 12.8 1.0 14.5 1.0 15.5 t plh t phl propagation delay time clear to q 2.7 15 7.9 15.0 1.0 18.5 1.0 19.5 ns 2.7 50 10.4 18.5 1.0 22.0 1.0 23.0 3.3 (*) 15 6.2 9.7 1.0 11.5 1.0 12.5 3.3 (*) 50 8.7 13.2 1.0 15.0 1.0 16.0 t wl clear pulse width, high 2.7 6.5 7.5 7.5 ns 3.3 (*) 5.0 5.0 5.0 t w clock pulse width 2.7 6.5 7.5 7.5 ns 3.3 (*) 5.0 5.0 5.0 t s setup time q to clock high or low 2.7 7.5 8.5 8.5 ns 3.3 (*) 5.0 6.0 6.0 t h hold time q to clock high or low 2.7 0.0 0.0 0.0 ns 3.3 (*) 0.0 0.0 0.0 t rem recovery time clear to q 2.7 4.5 4.5 ns 3.3 (*) 3.0 3.0 f max maximum clock frequency 2.7 15 65 130 55 mhz 2.7 50 45 60 40 3.3 (*) 15 115 180 95 3.3 (*) 50 65 95 55 t oslh t oshl output to output skew time (note1, 2) 2.7 50 0.5 1.0 1.5 1.5 ns 3.3 (*) 50 0.5 1.0 1.5 1.5
74lvx174 5/12 table 9: capacitive characteristics 1) c pd is defined as the value of the ic?s internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /n (per circuit) figure 4: test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r t = z out of pulse generator (typically 50 ? ) figure 5: waveform - propagation delays (f=1mhz; 50% duty cycle) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 3.3 5 10 10 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz 23 pf
74lvx174 6/12 figure 6: waveform - propagation delays, setup and hold times (f=1mhz; 50% duty cycle) figure 7: waveform - recovery time, minimum pulse width (f=1mhz; 50% duty cycle)
74lvx174 7/12 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.25 0.004 0.010 a2 1.64 0.063 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data 0016020d
74lvx174 8/12 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0? 8?0? 8? l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
74lvx174 9/12 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 6.45 6.65 0.254 0.262 bo 10.3 10.5 0.406 0.414 ko 2.1 2.3 0.082 0.090 po 3.9 4.1 0.153 0.161 p 7.9 8.1 0.311 0.319 tape & reel so-16 mechanical data
74lvx174 10/12 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 6.7 6.9 0.264 0.272 bo 5.3 5.5 0.209 0.217 ko 1.6 1.8 0.063 0.071 po 3.9 4.1 0.153 0.161 p 7.9 8.1 0.311 0.319 tape & reel tssop16 mechanical data
74lvx174 11/12 table 10: revision history date revision description of changes 27-aug-2004 3 ordering codes revision - pag. 1.
74lvx174 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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